Design Method of Variable-Latency Circuit with Tunable Approximate Completion-Detection Mechanism

Advanced information-processing services such as computer vision require a high-performance digital circuit to perform high-load processing at high speed. To achieve high-speed processing, several image-processing applications use an approximate computing technique reduce idle time of the circuit. However, it is difficult design while controlling error rate so not degrade service quality, and this used for only few applications. In paper, we propose method that achieves effectively in which each task changed by roughly detecting its completion. Using method, with low can be designed. The controllable, minimize also presented paper. confirm effectiveness our proposal, ripple-carry adder (RCA), 2-dimensional discrete cosine transform (2D-DCT) circuit, histogram oriented gradients (HOG) feature calculation are evaluated. Effective clock periods these circuits obtained around 1% improved about 64%, 6%, 12%, respectively, compared without error. Furthermore, impact miscalculation on video monitoring using object detection application investigated. As result, more than 99% points required detected, confirmed hardly degrades quality.